1. Field of the Invention
The present invention relates generally to the field of self-test structures for communications devices such as transceivers, and more particularly, a system for testing complex integrated circuit communications transceiver devices.
2. Discussion of the Prior Art
Transceiver circuits used in network communication applications, e.g., Ethernet, are designed and built as stand-alone chips with a standardized digital communications port for connection to the digital domain. Due to their stand-alone nature, and the relative simplicity of early transceivers, it was relatively simple to test these chips functionally to verify both the logic portion of the chip, and the analog transmit and receive circuitry. Early transceivers were built using a current driving, wave shaping, digital-to-analog converter as a transmitter and multiple analog comparators as a receiver. Due to their relative simplicity, these structures could alternatively be tested by parts when integrated into a larger piece of silicon with the digital portion being tested via Level-Sensitive Scan Design ("LSSD"), the DAC portion being tested through a series of DC parametric measurements, and the receiver being tested through a latched receiver test.
As the speed and complexity of the transceiver circuits increases, however, so does the complexity of the receiver. Moreover, the complexity of the receiver increases at a faster rate than the complexity of the transmitter and the digital circuitry. The transmitter and the digital circuitry both may still be tested via traditional LSSD and parametric means with little test coverage impact. Newer receivers, however, generally contain variable equalization and gain circuity, PLL driven clock recovery, peak detection, and AC coupled input circuitry with internal DC restoration which makes testing via DC parametric levels ineffectual. As a result, not only has functional test been required to verify the operation of the receiver, but such testing has generally needed to be performed over multiple cable lengths to insure that the equalization and gain range of the receiver can mitigate both signal loss and signal (primarily phase) distortion caused by varying lengths of cable over which the signal may travel.
FIG. 1 illustrates a data flow for an industry standard test methodology 10 such as described in the reference "ICS 1890 Test Plan Revision 3.0" .COPYRGT.1996 Integrated Circuit Systems, Inc. In this prior art method, all portions of the stand-alone transceiver chip are tested functionally at speed with repeated tests over multiple cable lengths, e.g, 1m-100m of cable, to test the ability of the device to adapt to, and successfully receive signals transmitted over varying lengths of cable. As shown in FIG. 1, the digital patterns from the tester (not shown) are input to the digital portion 15 of the transceiver under test, which generates signals for testing the analog transmitter portion 20. Outputs from the analog transmit portion 20 are current signals 21 which are input into passive components 23a and coil (magnetic) step-up module 24a for converting the current signals 21 into voltage signals suitable for input to the analog receiver portion 40 of the transceiver device. Depending upon the test, these analog voltage test signals are transmitted to the receiver 40 via variable length coaxial cables 30 having a pair of RJ45 connectors 25a,b and corresponding passive components 23b and step-down coil (magnetic) modules 24b for converting the test signals into the proper input signals 26 for the analog receiver.
The reference entitled "System and Method for Analog Test and Trimming of a Transceiver Circuit," IBM Disclosure BU8-97-0336, 1997, describes an earlier test methodology 80, the likes of which is illustrated in FIG. 2. Using this methodology, analog signals brought into the transceiver and converted to digital signatures via RX port 81 could be sampled by register 82 at appropriate intervals during a test window. Composite samples stored in 82 may be selected as data input to the transmitter portion of the transceiver 86 via mux structure 85 and control logic 88. Measurement using external test equipment of the analog waveforms produced by transmitter 86 respondent to register 82 contents provides a means of both assessing the function of the receiver 81 via analog output measurement, and providing analog feedback to monitor resistor trimming processes common in the tuning of analog integrated circuits. Additionally, a method allowing transmitter 86 to alternately source analog test data which may be provided by a built-in-self-test (BIST) to the receiver 81 via an optional external connection 89 and provide analog signatures for the verification of receiver 81 using sampling register 82 and control logic 88 is described. The methodology also adds Mux Latches 83 to provide for digital test stimulus for the bulk of the receive digital function 84, and a built-in-self-test unit 87 to provide data patterns, primarily for analog verification of the transmitter 86. Other digital portions of the transceiver, not shown, are tested using standard digital methodologies such as level-sensitive-scan-design (LSSD), scannable flip-flops, or functional patterns.
A prior art test methodology implemented for IBM's 10T Ethernet core is illustrated in FIG. 3(a). As shown in FIG. 3(a), the transceiver device 50 is segmented into a receive portion 65, a transmit portion 70, and a digital portion 16 comprising a transceiver digital logic device 15, transmit BIST logic device 63 and mux/latch boundaries devices 60a and 60b, each device being tested separately. The digital portion 16 is tested via LSSD means with mux/latch boundaries 60a and 60b providing alternate stimulus at the analog-to-digital boundary and digital data sampling at the digital-to-analog boundary respectively. The transmitter 70 is tested via parametric measurement (i.e. current or voltage) with patterns driven by a transmit counter/built-in-self-test (BIST). The receiver 65 is tested via a latch receiver test similar in nature to ASIC receivers whereby the digital results of analog-to-digital conversion performed by receiver 65 on DC input signals are captured at the mux/latch boundary 60a for scanout and verification via the tester.
FIG. 3(b) illustrates a test methodology for the IBM token ring transceiver embedded into a silicon chip which includes an on-chip analog loop back path 72 including a transfer gate 73 for providing an internal bridge between the analog transmitter 70' and receiver 65' in the circuit and used to test the receiver portion of the circuit.
In addition to the references cited above, U.S. Pat. Nos. 5,337,316, 5,402,440, 5,648,972 and 5,675,588 each described methodologies for testing communications devices, with U.S. Pat. No. 5,648,972 particularly directed to testing of a single integrated circuit transceiver.
Functional single IC transceiver testing of the nature as shown in FIG. 1, uses the transmitter portion to drive the receiver and requires complex board design to include passive components and coaxial connectors, as well as the ability to switch in and out coaxial cable lengths from 1 meter to more than 100 meters in order to "generate" the receive signal used for test. Generally, because the circuit is allowed to auto-converge to an equalization and gain setting, the test time for each cable length is greatly increased, e.g., to more than four seconds, while the data collection and verification methodology becomes complex, requiring either on-board or on-tester data collection and post-processing to handle the variable latency of the different cable lengths and the high data rate of the communications port. These factors make implementation of this test methodology in a digital test manufacturing environment extremely difficult, especially when multiple port counts which may exceed twelve (12) are contained within a single piece of silicon.
Thus, the need exists to test such chips in an inexpensive manufacturing test setting which provides a means of receiver test while eliminating requirements for external coaxial cable and external data collection and post-processing.